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1. general description the pca8574/74a provide general purpose remote i/o expansion for most microcontroller families via the two-line bidirectional i 2 c-bus (serial clock (scl), serial data (sda)). the devices consist of an 8-bit quasi-bidirectional port and an i 2 c-bus interface. the pca8574/74a have low current consumption and include latched outputs with 25 ma high current drive capability for directly driving leds. the pca8574/74a also possess an interrupt line ( int) that can be connected to the interrupt logic of the microcontroller. by sending an interrupt signal on this line, the remote i/o can inform the microcontroller if there is incoming data on its ports without having to communicate via the i 2 c-bus. the internal power-on reset (por) initializes the i/os as inputs. 2. features n 400 khz i 2 c-bus interface n 2.3 v to 5.5 v operation with 5.5 v tolerant i/os n 8-bit remote i/o pins that default to inputs at power-up n latched outputs with 25 ma sink capability for directly driving leds n total package sink capability of 200 ma n active low open-drain interrupt output n 8 programmable slave addresses using 3 address pins n readable device id (manufacturer, device type, and revision) n low standby current (10 m a max.) n - 40 c to +85 c operation n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma n packages offered: dip16, so16, tssop16, ssop20 3. applications n led signs and displays n servers n industrial control n medical equipment n plcs pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt rev. 02 14 may 2007 product data sheet
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 2 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt n cellular telephones n gaming machines n instrumentation and test measurement 4. ordering information 5. block diagram table 1. ordering information type number topside mark package name description version pca8574d pca8574d so16 plastic small outline package; 16 leads; body width 7.5 mm sot162-1 pca8574ad pca8574ad pca8574n pca8574n dip16 plastic dual in-line package; 16 leads (300 mil); long body sot38-1 pca8574an pca8574an pca8574pw pca8574 tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 pca8574apw pa8574a pca8574ts pca8574 ssop20 plastic shrink small outline package; 20 leads; body width 4.4 mm sot266-1 pca8574ats pca8574a fig 1. block diagram of pca8574/74a 002aac677 int i 2 c-bus control interrupt logic pca8574 pca8574a lp filter ad0 ad1 ad2 input filter shift register sda scl 8 bits write pulse read pulse power-on reset v dd v ss i/o port p0 to p7
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 3 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 6. pinning information 6.1 pinning fig 2. simpli?ed schematic diagram of p0 to p7 002aac109 write pulse read pulse d ci s ff q power-on reset data from shift register i trt(pu) 100 m a i oh i ol v dd p0 to p7 v ss d ci s ff q data to shift register to interrupt logic fig 3. pin con?guration for dip16 fig 4. pin con?guration for so16 pca8574n pca8574an ad0 v dd ad1 sda ad2 scl p0 int p1 p7 p2 p6 p3 p5 v ss p4 002aac679 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 pca8574d pca8574ad ad0 v dd ad1 sda ad2 scl p0 int p1 p7 p2 p6 p3 p5 v ss p4 002aac678 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 4 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 6.2 pin description fig 5. pin con?guration for tssop16 fig 6. pin con?guration for ssop20 pca8574pw pca8574apw ad0 v dd ad1 sda ad2 scl p0 int p1 p7 p2 p6 p3 p5 v ss p4 002aac941 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 pca8574ts pca8574ats int p7 scl p6 n.c. n.c. sda p5 v dd p4 ad0 v ss ad1 p3 n.c. n.c. ad2 p2 p0 p1 002aac680 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 table 2. pin description for dip16, so16, tssop16 symbol pin description ad0 1 address input 0 ad1 2 address input 1 ad2 3 address input 2 p0 4 quasi-bidirectional i/o 0 p1 5 quasi-bidirectional i/o 1 p2 6 quasi-bidirectional i/o 2 p3 7 quasi-bidirectional i/o 3 v ss 8 supply ground p4 9 quasi-bidirectional i/o 4 p5 10 quasi-bidirectional i/o 5 p6 11 quasi-bidirectional i/o 6 p7 12 quasi-bidirectional i/o 7 int 13 interrupt output (active low) scl 14 serial clock line sda 15 serial data line v dd 16 supply voltage
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 5 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt table 3. pin description for ssop20 symbol pin description int 1 interrupt output (active low) scl 2 serial clock line n.c. 3 not connected sda 4 serial data line v dd 5 supply voltage ad0 6 address input 0 ad1 7 address input 1 n.c. 8 not connected ad2 9 address input 2 p0 10 quasi-bidirectional i/o 0 p1 11 quasi-bidirectional i/o 1 p2 12 quasi-bidirectional i/o 2 n.c. 13 not connected p3 14 quasi-bidirectional i/o 3 v ss 15 supply ground p4 16 quasi-bidirectional i/o 4 p5 17 quasi-bidirectional i/o 5 n.c. 18 not connected p6 19 quasi-bidirectional i/o 6 p7 20 quasi-bidirectional i/o 7
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 6 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 7. functional description refer to figure 1 bloc k diag r am of pca8574/74a . 7.1 device address following a start condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). the address of the pca8574/74a is shown in figure 7 . slave address pins ad2, ad1, and ad0 choose 1 of 8 slave addresses. to conserve power, no internal pull-up resistors are incorporated on ad2, ad1, and ad0. address values depending on ad2, ad1, and ad0 can be found in t ab le 4 pca8574 address map and t ab le 5 pca8574a address map . remark: when using the pca8574a, the general call address (0000 0000b) and the device id address (1111 100xb) are reserved and cannot be used as device address. failure to follow this requirement will cause the pca8574a not to acknowledge. the last bit of the ?rst byte de?nes the operation to be performed. when set to logic 1 a read is selected, while a logic 0 selects a write operation. when ad2, ad1 and ad0 are held to v dd or v ss , the same address as the pcf8574 or pcf8574a is applied. 7.1.1 address maps fig 7. pca8574/74a address r/w 002aab636 a6 a5 a4 a3 a2 a1 a0 programmable slave address table 4. pca8574 address map a6 a5 a4 a3 a2 a1 a0 address 010000020h 010000121h 010001022h 010001123h 010010024h 010010125h 010011026h 010011127h
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 7 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 8. i/o programming 8.1 quasi-bidirectional i/o architecture the pca8574/74as 8 ports (see figure 2 ) are entirely independent and can be used either as input or output ports. input data is transferred from the ports to the microcontroller in the read mode (see figure 9 ). output data is transmitted to the ports in the write mode (see figure 8 ). this quasi-bidirectional i/o can be used as an input or output without the use of a control signal for data directions. at power-on the i/os are high. in this mode only a current source (i oh ) to v dd is active. an additional strong pull-up to v dd (i trt(pu) ) allows fast rising edges into heavily loaded outputs. these devices turn on when an output is written high, and are switched off by the negative edge of scl. the i/os should be high before being used as inputs. after power-on, as all the i/os are set high, all of them can be used as inputs. any change in setting of the i/os as either inputs or outputs can be done with the write mode. remark: if a high is applied to an i/o which has been written earlier to low, a large current (i ol ) will ?ow to v ss . 8.2 writing to the port (output mode) to write, the master (microcontroller) ?rst addresses the slave device. by setting the last bit of the byte containing the slave address to logic 0 the write mode is entered. the pca8574/74a acknowledges and the master sends the data byte for p7 to p0 and is acknowledged by the pca8574/74a. the 8-bit data is presented on the port lines after it has been acknowledged by the pca8574/74a. the number of data bytes that can be sent successively is not limited. the previous data is overwritten every time a data byte has been sent. table 5. pca8574a address map a6 a5 a4 a3 a2 a1 a0 address 011100038h 011100139h 01110103ah 01110113bh 01111003ch 01111013dh 01111103eh 01111113fh
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 8 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 8.3 reading from a port (input mode) all ports programmed as input should be set to logic 1. to read, the master (microcontroller) ?rst addresses the slave device after it receives the interrupt. by setting the last bit of the byte containing the slave address to logic 1 the read mode is entered. the data bytes that follow on the sda are the values on the ports. if the data on the input port changes faster than the master can read, this data may be lost. fig 8. write mode (output) a5 a4 a3 a2 a1 a0 0 a sa6 slave address start condition r/w acknowledge from slave 002aac120 p6 1 p7 data 1 a acknowledge from slave 12345678 scl 9 sda a acknowledge from slave write to port data output from port t v(q) p5 data 2 data 2 valid p4 p3 p2 p1 p0 p7 p4 p3 p2 p1 p0 0 p5 p5 t v(q) data 1 valid p5 output voltage i trt(pu) i oh p5 pull-up output current t d(rst) int a low-to-high transition of sda while scl is high is de?ned as the stop condition (p). transfer of data can be stopped at any moment by a stop condition. when this occurs, data present at the last acknowledge phase is valid (output mode). input data is lost. fig 9. read input port register a5 a4 a3 a2 a1 a0 1 a sa6 slave address start condition r/w acknowledge from slave 002aac121 data from port a acknowledge from master sda 1 no acknowledge from master read from port data into port data from port data 1 data 4 int data 4 data 2 data 3 p stop condition t v(q) t d(rst) t h(d) t su(d) t d(rst)
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 9 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 8.4 power-on reset when power is applied to v dd , an internal power-on reset (por) holds the pca8574/74a in a reset condition until v dd has reached v por . at that point, the reset condition is released and the pca8574/74a registers and i 2 c-bus/smbus state machine will initialize to their default states. thereafter v dd must be lowered below 0.2 v to reset the device. 8.5 interrupt output ( int) the pca8574/74a provides an open-drain interrupt ( int) which can be fed to a corresponding input of the microcontroller (see figure 8 , figure 9 , and figure 10 ). this gives these chips a kind of master function which can initiate an action elsewhere in the system. an interrupt is generated by any rising or falling edge of the port inputs. after time t v(d) the signal int is valid. the interrupt disappears when data on the port is changed to the original setting or data is read from or written to the device which has generated the interrupt. in the write mode, the interrupt may become deactivated (high) on the rising edge of the write to port pulse. on the falling edge of the write to port pulse the interrupt is de?nitely deactivated (high). the interrupt is reset in the read mode on the rising edge of the read from port pulse. during the resetting of the interrupt itself, any changes on the i/os may not generate an interrupt. after the interrupt is reset any change in i/os will be detected and transmitted as an int. fig 10. application of multiple pca8574s with interrupt 002aac682 v dd microcomputer int pca8574 int pca8574 int device 1 device 2 pca8574 int device 8
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 10 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 9. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 9.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 11 ). 9.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is de?ned as the start condition (s). a low-to-high transition of the data line while the clock is high is de?ned as the stop condition (p) (see figure 12 .) 9.2 system con?guration a device generating a message is a transmitter; a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 13 ). fig 11. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 12. de?nition of start and stop conditions mba608 sda scl p stop condition sda scl s start condition
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 11 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 9.3 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse; set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig 13. system con?guration 002aaa966 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c-bus multiplexer slave fig 14. acknowledgement on the i 2 c-bus 002aaa987 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 12 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 10. application design-in information 10.1 bidirectional i/o expander applications in the 8-bit i/o expander application shown in figure 15 , p0 and p1 are inputs, and p2 to p7 are outputs. when used in this con?guration, during a write, the input (p0 and p1) must be written as high so the external devices fully control the input ports. the desired high or low logic levels may be written to the i/os used as outputs (p2 to p7). during a read, the logic levels of the external devices driving the input ports (p0 and p1) and the previous written logic level to the output ports (p2 to p7) will be read. the gpio also has an interrupt line ( int) that can be connected to the interrupt logic of the microprocessor. by sending an interrupt signal on this line, the remote i/o informs the microprocessor that there is incoming data or a change of data on its ports without having to communicate via the i 2 c-bus. 10.2 high current-drive load applications the gpio has a maximum sinking current of 25 ma per bit. in applications requiring additional drive, two port pins in the same octal may be connected together to sink up to 50 ma current. both bits must then always be turned on or off together. up to 8 pins (one octal) can be connected together to drive 200 ma. fig 15. bidirectional i/o expander application 002aac123 v dd temperature sensor battery status control for latch control for switch control for audio control for camera control for mp3 p0 p1 p2 p3 p4 p5 p6 p7 v dd sda scl int ad0 ad1 ad2 core processor v dd fig 16. high current-drive load application 002aac124 v dd p0 p1 p2 p3 p4 p5 p6 p7 v dd sda scl int ad0 ad1 ad2 core processor v dd load
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 13 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 11. limiting values [1] total package (maximum) output current is 400 ma. table 6. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.5 +6 v i dd supply current - 100 ma i ss ground supply current - 400 ma v i input voltage v ss - 0.5 5.5 v i i input current - 20 ma i o output current [1] - 50 ma p tot total power dissipation - 400 mw p/out power dissipation per output - 100 mw t stg storage temperature - 65 +150 c t amb ambient temperature operating - 40 +85 c
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 14 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 12. static characteristics [1] the power-on reset circuit resets the i 2 c-bus logic with v dd pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 15 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 13. dynamic characteristics [1] t vd;ack = time for acknowledgement signal from scl low to sda (out) low. [2] t vd;dat = minimum time for sda data out to be valid following scl low. [3] a master device must internally provide a hold time of at least 300 ns for the sda signal (refer to the v il of the scl signal) in order to bridge the unde?ned region scls falling edge. [4] the maximum t f for the sda and scl bus lines is speci?ed at 300 ns. the maximum fall time for the sda output stage t f is speci?ed at 250 ns. this allows series protection resistors to be connected between the sda and the scl pins and the sda/scl bus lines witho ut exceeding the maximum speci?ed t f . [5] c b = total capacitance of one bus line in pf. [6] input ?lters on the sda and scl inputs suppress noise spikes less than 50 ns. table 8. dynamic characteristics v dd = 2.3 v to 5.5 v; v ss =0v; t amb = - 40 cto+85 c; unless otherwise speci?ed. limits are for fast-mode i 2 c-bus. symbol parameter conditions min typ max unit f scl scl clock frequency 0 - 400 khz t buf bus free time between a stop and start condition 1.3 - - m s t hd;sta hold time (repeated) start condition 0.6 - - m s t su;sta set-up time for a repeated start condition 0.6 - - m s t su;sto set-up time for stop condition 0.6 - - m s t hd;dat data hold time 0 - - ns t vd;ack data valid acknowledge time [1] 0.1 - 0.9 m s t vd;dat data valid time [2] 50 - - ns t su;dat data set-up time 100 - - ns t low low period of the scl clock 1.3 - - m s t high high period of the scl clock 0.6 - - m s t f fall time of both sda and scl signals [3] [4] 20 + 0.1c b [5] - 300 ns t r rise time of both sda and scl signals 20 + 0.1c b [5] - 300 ns t sp pulse width of spikes that must be suppressed by the input ?lter [6] - - 50 ns port timing; c l 100 pf (see figure 8 and figure 9 ) t v(q) data output valid time - - 4 m s t su(d) data input set-up time 0 - - m s t h(d) data input hold time 4 - - m s interrupt timing; c l 100 pf (see figure 8 and figure 9 ) t v(d) data input valid time - - 4 m s t d(rst) reset delay time - - 4 m s
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 16 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt rise and fall times refer to v il and v ih . fig 17. i 2 c-bus timing diagram scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 002aab175 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) 1 /f scl t r t vd;dat
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 17 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 14. package outline fig 18. package outline sot38-1 (dip16) unit a max. 1 2 b 1 cee m h l references outline version european projection issue date iec jedec jeita mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot38-1 99-12-27 03-02-13 a min. a max. b max. w m e e 1 1.40 1.14 0.055 0.045 0.53 0.38 0.32 0.23 21.8 21.4 0.86 0.84 6.48 6.20 0.26 0.24 3.9 3.4 0.15 0.13 0.254 2.54 7.62 0.3 8.25 7.80 0.32 0.31 9.5 8.3 0.37 0.33 2.2 0.087 4.7 0.51 3.7 0.15 0.021 0.015 0.013 0.009 0.01 0.1 0.02 0.19 050g09 mo-001 sc-503-16 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 16 1 9 8 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. (1) (1) d (1) z dip16: plastic dual in-line package; 16 leads (300 mil); long body sot38-1
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 18 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt fig 19. package outline sot162-1 (so16) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 10.5 10.1 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot162-1 8 16 w m b p d detail x z e 9 1 y 0.25 075e03 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.41 0.40 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 x q a a 1 a 2 h e l p q e c l v m a (a ) 3 a 0 5 10 mm scale so16: plastic small outline package; 16 leads; body width 7.5 mm sot162-1 99-12-27 03-02-19
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 19 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt fig 20. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 20 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt fig 21. package outline sot266-1 (ssop20) unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0 1.4 1.2 0.32 0.20 0.20 0.13 6.6 6.4 4.5 4.3 0.65 1 0.2 6.6 6.2 0.65 0.45 0.48 0.18 10 0 o o 0.13 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 0.75 0.45 sot266-1 mo-152 99-12-27 03-02-19 w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a x (a ) 3 a y 0.25 110 20 11 pin 1 index 0 2.5 5 mm scale ssop20: plastic shrink small outline package; 20 leads; body width 4.4 mm sot266-1 a max. 1.5
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 21 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 15. handling information inputs and outputs are protected against electrostatic discharge in normal handling. however, to be completely safe you must take normal precautions appropriate to handling integrated circuits. 16. soldering 16.1 introduction there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. 16.2 through-hole mount packages 16.2.1 soldering by dipping or by solder wave typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the speci?ed maximum storage temperature (t stg(max) ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 16.2.2 manual soldering apply the soldering iron (24 v or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 c and 400 c, contact may be up to 5 seconds. 16.3 surface mount packages 16.3.1 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 22 ) than a pbsn process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 22 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 9 and 10 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 22 . for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . table 9. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 10. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 msl: moisture sensitivity level fig 22. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 23 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 16.3.2 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 16.3.3 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 c and 320 c. 16.4 package related soldering information table 11. suitability of ic packages for wave, re?ow and dipping soldering methods mounting package [1] soldering method wave re?ow [2] dipping through-hole mount cpga, hcpga suitable -- dbs, dip, hdip, rdbs, sdip, sil suitable [3] - suitable through-hole-surface mount pmfp [4] not suitable not suitable -
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 24 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your nxp semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vapori zation of the moisture in them (the so called popcorn effect). [3] for sdip packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [4] hot bar soldering or manual soldering is suitable for pmfp packages. [5] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [6] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot pene trate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposite d on the heatsink surface. [7] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [8] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [9] wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [10] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil . however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropri ate soldering pro?le can be provided on request. surface mount bga, htsson..t [5] , lbga, lfbga, sqfp, ssop..t [5] , tfbga, vfbga, xson not suitable suitable - dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [6] suitable - plcc [7] , so, soj suitable suitable - lqfp, qfp, tqfp not recommended [7] [8] suitable - ssop, tssop, vso, vssop not recommended [9] suitable - cwqccn..l [10] , wqccn..l [10] not suitable not suitable - table 11. suitability of ic packages for wave, re?ow and dipping soldering methods continued mounting package [1] soldering method wave re?ow [2] dipping
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 25 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 17. abbreviations 18. revision history table 12. abbreviations acronym description cdm charged device model cmos complementary metal oxide semiconductor esd electrostatic discharge gpio general purpose input/output hbm human body model led light emitting diode ic integrated circuit i 2 c-bus inter-integrated circuit bus id identi?cation lsb least signi?cant bit mm machine model msb most signi?cant bit plc programmable logic controller pwm pulse width modulation raid redundant array of independent disks smbus system management bus table 13. revision history document id release date data sheet status change notice supersedes pca8574_pca8574a_2 20070514 product data sheet - pca8574_pca8574a_1 modi?cations: ? section 2 f eatures , last bullet item: changed tssop20 to tssop16 ? t ab le 1 order ing inf or mation : changed package from tssop20 (sot360-1) to tssop16 (sot403-1) ? section 6.1 pinning : deleted pin con?guration for tssop20; added pin con?guration for tssop16 ? t ab le 2 title changed (added tssop16) ? t ab le 3 title changed (deleted tssop20) ? section 14 p ac kage outline : changed package from tssop20 (sot360-1) to tssop16 (sot403-1) pca8574_pca8574a_1 20070117 product data sheet - -
pca8574_pca8574a_2 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 02 14 may 2007 26 of 27 nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 19.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 19.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 19.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 20. contact information for additional information, please visit: http://www .nxp.com for sales of?ce addresses, send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors pca8574/74a remote 8-bit i/o expander for i 2 c-bus with interrupt ? nxp b.v. 2007. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 14 may 2007 document identifier: pca8574_pca8574a_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.1 address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 i/o programming . . . . . . . . . . . . . . . . . . . . . . . . 7 8.1 quasi-bidirectional i/o architecture . . . . . . . . . 7 8.2 writing to the port (output mode) . . . . . . . . . . . 7 8.3 reading from a port (input mode) . . . . . . . . . . 8 8.4 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.5 interrupt output ( int) . . . . . . . . . . . . . . . . . . . . 9 9 characteristics of the i 2 c-bus. . . . . . . . . . . . . 10 9.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9.1.1 start and stop conditions . . . . . . . . . . . . . 10 9.2 system con?guration . . . . . . . . . . . . . . . . . . . 10 9.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 11 10 application design-in information . . . . . . . . . 12 10.1 bidirectional i/o expander applications . . . . . 12 10.2 high current-drive load applications . . . . . . . . 12 11 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 12 static characteristics. . . . . . . . . . . . . . . . . . . . 14 13 dynamic characteristics . . . . . . . . . . . . . . . . . 15 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 15 handling information. . . . . . . . . . . . . . . . . . . . 21 16 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 21 16.2 through-hole mount packages . . . . . . . . . . . . 21 16.2.1 soldering by dipping or by solder wave . . . . . 21 16.2.2 manual soldering . . . . . . . . . . . . . . . . . . . . . . 21 16.3 surface mount packages . . . . . . . . . . . . . . . . 21 16.3.1 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 21 16.3.2 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23 16.3.3 manual soldering . . . . . . . . . . . . . . . . . . . . . . 23 16.4 package related soldering information . . . . . . 23 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 19 legal information . . . . . . . . . . . . . . . . . . . . . . 26 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 26 19.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 19.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 26 19.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 26 20 contact information . . . . . . . . . . . . . . . . . . . . 26 21 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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